One aim is the compact and efficient generation of highly stable signals in the millimeter-wave range. Those signals are required to realize radar sensors with high resolution and accuracy.

For signal generations using PLLs, a low frequency reference oscillator (in the MHz domain), as well as a voltage-controlled radio frequency (RF) oscillator (VCO) are required. A fraction of the RF signal is coupled out and frequency divided. Afterwards, the phase of the divided signal is compared to the reference signal’s phase. By varying the control voltage of the VCO, the phase of the RF oscillators is locked to the reference. The properties (frequency-stability, phase noise) of the RF signal are derived from the reference signal. The required system performance has to be taken into account when choosing the reference oscillator. The frequency-stability is decreased by the frequency multiplication factor (N) and the phase noise is increased by 20·log(N). For this reason, the reference frequency should be chosen to be as high as possible, to minimize the performance loss. Available PLLs support reference frequencies up to 100 MHz. Due to the frequency division of the RF signal, a PLL-based synthesizer is not directly limited to a maximum RF frequency, so that the output frequency of the VCO can be chosen high enough, to ease the suppression of harmonics after frequency multiplication. Furthermore, the loop filter of the control voltage of the RF VCO will suppress the reference signal, to avoid influences of the reference in the output spectrum.

To generate frequency chirps, which are required for frequency modulated continuous wave (FMCW) radar applications, both concepts, DDS and PLL, are feasible.

^{rd} order passive loop filter. The RF signal is first of all doubled in frequency. Afterwards, the power level is adapted to the MMIC input requirements using a variable attenuator. A further x6 frequency multiplication into W‑band is performed on chip.