Signal Generation

Due to the properties of a high electron mobility transistor (HEMT), a HEMT is not suitable for the generation of frequency-stable signals. The higher 1/f noise (compared to bipolar transistor) technology increases the phase noise of HEMT-based oscillators, which lowers the signal quality. Given that the monolithic microwave integrated circuits (MMICs) processed at Fraunhofer‑IAF are based on a metamorphic HEMT technology, a direct integration of the oscillator on the MMIC is not feasible. Therefore, a concept is used, which contains of a lower frequency signal generation with adjacent frequency multiplication. As a low frequency signal source, either a direct digital synthesizer or a phase-locked loop can be used.

Due to the direct signal synthesis using fast analog-to-digital converters, commercially available DDS-chips are limited to a relatively low output frequency of about 1.5 GHz. To generate W-band signals out of a DDS-based concept, a high frequency multiplication factor of about 100 is necessary. The low output frequency makes the suppression of unwanted harmonics after frequency multiplication more difficult and limit the quality of the transmit bandwidth.

For signal generations using PLLs, a low frequency reference oscillator (in the MHz domain), as well as a voltage-controlled radio frequency (RF) oscillator (VCO) are required. A fraction of the RF signal is coupled out and frequency divided. Afterwards, the phase of the divided signal is compared to the reference signal’s phase. By varying the control voltage of the VCO, the phase of the RF oscillators is locked to the reference. The properties (frequency-stability, phase noise) of the RF signal are derived from the reference signal. The required system performance has to be taken into account when choosing the reference oscillator. The frequency-stability is decreased by the frequency multiplication factor (N) and the phase noise is increased by 20·log(N). For this reason, the reference frequency should be chosen to be as high as possible, to minimize the performance loss. Available PLLs support reference frequencies up to 100 MHz. Due to the frequency division of the RF signal, a PLL-based synthesizer is not directly limited to a maximum RF frequency, so that the output frequency of the VCO can be chosen high enough, to ease the suppression of harmonics after frequency multiplication. Furthermore, the loop filter of the control voltage of the RF VCO will suppress the reference signal, to avoid influences of the reference in the output spectrum.

To generate frequency chirps, which are required for frequency modulated continuous wave (FMCW) radar applications, both concepts, DDS and PLL, are feasible.

Due to the low output frequency of DDS-synthesizers and the resulting complexity to suppress harmonics generated by frequency multiplication, a PLL-based concept for signal generation is used. To generate linear FMCW frequency chirps, a PLL with fractional divider is used, whereby the division factor can be varied linearly during a ramp. A 100 MHz reference oscillator with high frequency-stability and low phase noise is used. The RF VCO is working at 7.8 GHz and can be tuned between 7.2 GHz and 8.3 GHz using a 3^rd order passive loop filter. The RF signal is first of all doubled in frequency. Afterwards, the power level is adapted to the MMIC input requirements using a variable attenuator. A further x6 frequency multiplication into W‑band is performed on chip.

Due to the frequency multiplication by 12 of the PLL-stabilized signal, a frequency range from 86.4 GHz to 99.6 GHz is covered, allowing a radar bandwidth of more than 10 GHz. The dynamically changeable frequency divider of the PLL allows a very precise generation of linear frequency chirps, which are furthermore characterized by a high repeatability.

Further Information:

3.5 GSPS Direct Digital Synthesizer with 12-bit DAC

8 GHz Fractional-N PLL with Sweeper

Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer